In contrast to traditional planar metal-oxide-semiconductor field-effect transistors (MOSFETS), which are fabricated using conventional lithographic fabrication methods, nonplanar FETs (Field-Effect Transistors) incorporate various vertical transistor structures, and typically include two or more gate structures formed in parallel. One such semiconductor structure is the “FinFET” which takes its name from the multiple thin silicon “fins” that are used to form the respective gate channels, and which are typically on the order of tens of nanometers in width.
More particularly, referring to the exemplary prior art nonplanar MOS transistor having a FinFET configuration shown in FIG. 1, a FinFET device 10 generally includes one or more parallel silicon fin structures (or simply “fins”) 12. The fins extend between a common source electrode and a common drain electrode (not shown in FIG. 1). A conductive gate structure 16 “wraps around” three sides of both fins, and is separated from the fins by a standard gate insulator layer 18. Fins may be suitably doped to produce the desired FET polarity, as is known in the art, such that a gate channel is formed within the near surface of the fins adjacent to the gate insulator 18.
Fin structures (and thus FinFET devices) may be formed on a semiconductor substrate. The semiconductor substrate may be a silicon on insulator (SOI) wafer (not shown). The silicon on insulator (SOI) wafer comprises a silicon-comprising material layer overlying a silicon oxide layer. Fin structures are formed from the silicon-comprising material layer The SOI wafer is supported by a support substrate.
Alternatively, the semiconductor substrate may be a bulk silicon wafer from which the fin structures are formed. The bulk silicon wafer comprises a monolithic block of single crystal silicon. A FinFET device formed from a bulk silicon wafer is referred to herein as a “bulk FinFET device”.
Electrical isolation between adjacent fins and between the source and drain electrodes of unrelated FinFET devices is needed. “Unrelated” as used herein means that the devices are not intended to be coupled together. Electrical current leakage is a parasitic effect, which degrades performance of an integrated circuit (IC). When fin structures are formed from the silicon-comprising material layer of an SOI wafer, silicon and thus a conduction path are removed and thus electrical isolation between the fin structures and between unrelated source and drain electrodes is relatively easy.
However, isolating the fin structures and source and drain electrodes of unrelated FinFET devices on a bulk silicon wafer is more problematic as the silicon of the bulk silicon wafer (See e.g., FIG. 11) between the fin structures and source and drain regions forms a conduction path. Isolation trenches have been used to electrically isolate adjacent semiconductor devices formed in a semiconductor substrate. Typical isolation trenches may generally be formed by creating an isolation trench in the semiconductor substrate through an anisotropic etch process, filling the trench with a dielectric material, such as chemical vapor deposition (CVD) silicon oxide (SiO2) or the like, and removing the excess dielectric using a planarization process, such as chemical mechanical polishing (CMP).
In FinFET devices, deep trench isolation (DTI) is generally sought to provide adequate isolation between the source and drain electrodes of unrelated FinFET devices and to substantially prevent latch-up. Shallow trench isolation (STI) is generally used to provide isolation between fin structures. The formation and filling of isolation trenches to provide electrical isolation, particularly deep isolation trenches, is difficult because isolation trenches have high aspect ratios. Aspect ratio is the ratio of the depth of the opening to its width. Even state of the art oxide chemical vapor deposition (CVD) processes such as advanced high density plasma (HDP) or ozone based TEOS (tetraethylorthosilicate) processes cannot reliably fill these high aspect ratio isolation trenches. This causes problems in controlling and creating electrical isolation in bulk FinFET devices, particularly deep trench isolation.
Accordingly, it is desirable to provide methods for forming bulk FinFET devices having deep trench isolation (DTI) between source and drain electrodes of unrelated FinFET devices and to substantially prevent latch-up. In addition, it is desirable to provide methods for forming deep isolation trenches that reduce the number of processing steps conventionally required to form the bulk FinFET device. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.